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  apex microtechnology corporation ? telephone (520) 690-8600 ? fax (520) 888-3329 ? orders (520) 690-8601 ? email prodlit@apexmicrotech.com 1 p r e l i m i n a ry features ? delivers up to 5a continuous output ? operates at supply voltages up to 60v ? ttl and cmos compatible inputs ? no shoot-through current ? thermal shutdown (outputs off) at 160 c ? shorted load protection (to vs or pgnd or shorted load) ? no bootstrap capacitors required ? programmable onboard pwm applications ? dc motor drives ? position and velocity servomechanisms ? factory automation robots ? numerically controlled machinery ? computer printers and plotters ? audio amplification figure 1. block diagram description the SA56 is a 5a pwm amplifer designed for motion con - trol applications. the device is built using a multi-technology process which combines bipolar and cmos control circuitry with dmos power devices in the same monolithic structure. ideal for driving dc and stepper motors; the SA56 accom - modates peak output currents up to 10a. an innovative circuit which facilitates low-loss sensing of the output current has been implemented. on board pwm oscillator and comparator are used to convert an analog signal into pwm direction and magnitude for motor control applications, or to amplify audio signals using class d amplifcation. 23 pin sip p ac k age style ex 7ee 7 7t 7 (buf%sjwf boe $pouspm "065 #065 $pouspmmphjd boe 18.(fofsbups %*4"#-& %*3 5 -*. 4$ */ * 4&/ '"6-5 $ 18. 7 3&' 18. "obmph (/% 1pxfs (/%             )fbu5bc           ) 5 5 1    8 8 8  " 1 & 9 . * $ 3 0 5 & $ )  $ 0 .      
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apex microtechnology corporation ? 5980 north shannon road ? tucson, arizona 85741 ? usa ? applications hotline: 1 (800) 546-2739 2 p r e l i m i n a ry absolute maximum ratings specifications SA56 absolute maximum ratings supply voltage, v dd 5.5v supply voltage, v s 60v peak output current (100ms) 10a continuous output current 5a power dissipation tbd power dissipation (t a = 25c, free air) 3w junction temperature, t j(max) 150c esd susceptibility (logic signals only) 1500v storage temperature, t stg C40c to +150c lead temperature (soldering, 10 sec.) 300c junction temperature, t j C40c to +150c note: these specifcations apply for v s = 50v and v dd = 5v at 25 c, unless otherwise specifed. specifications parameter test conditions min typ max units v s 12 60 v vdd 4.5 5.5 v switch on resistance, r ds (on) output current = 5a 0.25 0.6 ? n-channel switch on resistance, r ds (on) output current = 5a 0.3 0.6 ? p-channel clamp diode forward drop, v clamp clamp current = 5a 1.43 tbd v logic low input voltage, v il -0.5 0.8 v logic low input current, i il v in = C0.1v -10 +10 a logic high input voltage, v ih 2 v dd v logic high input current, i ih v in = 5.5v -10 10 a current sense output i out = 1a 300 350 a i out = 5a 1.3 1.5 ma current sense linearity 1a i out 5a 1 5 % 100 ma i out 5a 8 % 5a i out 10a (peak currents only) 8 % shutdown temperature, t jsd outputs turn off 160 c quiescent supply current, i s no load, f sw = 23khz 50% duc 12 tbd ma quiescent supply current, i dd no load, f sw = 23khz 50% duc 6 15 ma output turn-on delay time, t don sourcing outputs, i out = 1a 61 ns sinking outputs, i out = 1a 66 ns output turn-on switching time, t on sourcing outputs, i out = 1a 51 ns sinking outputs, i out = 1a 51 ns output turn-off delay times, t doff sourcing outputs, i out = 1a 59 ns sinking outputs, i out = 1a 54 ns output turn-off switching time, t off sourcing outputs, i out = 1a 70 ns sinking outputs, i out = 1a 70 ns minimum input pulse width, t p 100 ns (digital mode) pwm frequency (digital mode) 500 khz reference voltage 2.4 2.5 2.6 v vref output current (vref 2.5v) source only, no current sink capability 1 ma analog input range for load current = 400a 1 4 v full modulation high current shutdown response output shorted 250 800 ns (no bypass capacitor at scin pin)
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apex microtechnology corporation ? telephone (520) 690-8600 ? fax (520) 888-3329 ? orders (520) 690-8601 ? email prodlit@apexmicrotech.com 5 p r e l i m i n a ry operating considerations SA56 general please read application note 1 "general operating consid - erations" which covers stability, power supplies, heat sinking, mounting, and specifcation interpretation. visit www.apexmi - crotech.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit, heat sink selection, apex's complete application notes library, technical seminar workbook and evaluation kits. ground pins there are 4 gnd pins. pins 9 & 10 are for input signal gnd and pins 1 and 23 are for power gnd. power supply bypassing bypass capacitors to power supply terminals vs and v dd must be connected physically close to the pins to prevent erratic, low effciency operation and excessive ringing at the outputs. electrolytic capacitors, at least 10f per output amp, are required for suppressing vs to pgnd noise. high qual - ity ceramic capacitors (x7r) 1f or greater should also be used. only capacitors rated for switching applications should be considered. the bypass capacitors must be located as close to the power supply pins as possible (due to the very fast switching times of the outputs, the inductance of 1 inch of circuit trace could cause noticeable degradation in performance). the bypassing requirements of v dd are less stringent, but still necessary. a 0.1f to 0.47f capacitor connected directly between the v dd and gnd (sig) pins will suffce. pin descriptions pin # name description 1,23 pgnd power ground, high current ground return path of the motor. 2,3 bout half bridge output b 4,5,19,20 vs high voltage supply 6 scin short circuit detect, cmos. this pin can be used as a fag for a short cir - cuit condition. under normal operation this pin will be logic low. when a short circuit is detected, or output current exceeds approximately 10a, this pin will change to logic high and the output will be latched off. grounding this pin disables short circuit protection. this pin should be left open if short circuit protection is desired but the fag is not used. short circuit protection functions independently of programmable current limit (isen). it is nessesary to bypass the scin pin with a 14-47pf ceramic capacitor. this capacitor will add a de - lay to the short circuit response but the device will still be able to protect itself against short circuit and over current. 7 tlim temperature limit, cmos. this pin can be used as a fag for an over temperature condition. under normal operation this pin will be logic low. when junction tem - perature exceeds approximately 160c this pin will change to logic high and the output will be latched off. ground - ing this pin disables over temperature protection. this pin should be left open if over temperature protection is desired but the fag is not used. 8 isen/ /ilim current sense output and program - mable current limit. a current propor - tional to output current is sourced by this pin. typically this pin is connected to a resistor for programmable current limit or transconductance operation. 9,10 gnd(sig) ground connection for all internal digital and low current analog circuitry. 11 fault protection circuit fag output, cmos. the fault pin will be logic high when the output mosfets have been automati - cally latched off because of a short circuit or over temperature condition. this pin should be left open if not used. 12 cpwm an external timing capacitor is connected to this pin to set the frequency of the internal oscillator and ramp generator for analog control mode. the capaci - tor value (pf) = 4.05x10 7 /f sw , where f sw = the desired switching frequency. this pin is grounded for digital control mode. 13,14 vdd 5v supply for input logic and low voltage analog circuitry. 15 vref reference voltage. can be used at low current for biasing analog loop circuits. 16 dir direction logic input, cmos/ttl. de - termines the active output mosfets in two quadrant digital control mode. this pin should be grounded for analog control mode. 17 pwm cmos/ttl input for digital pwm con - trol, or 1-4v analog input for duty cycle control in analog control mode. 18 disable disable logic input, cmos/ttl. logic low on this pin allows the SA56 to func - tion normally. when pulled to logic high, all four output mosfets are disabled. pulling this pin high, then low will reset a latched fault condition caused by a short circuit or over temperature fault. 21,22 aout half bridge output a
apex microtechnology corporation ? 5980 north shannon road ? tucson, arizona 85741 ? usa ? applications hotline: 1 (800) 546-2739 6 p r e l i m i n a ry operating considerations SA56 modes of operation the following chart shows the four modes of operation. mode cpwm pwm dir aout bout 2 quad digital gnd modu - lation in high high pwm 2 quad digital gnd modu - lation in low pwm high 4 quad digital gnd high modu - lated in dir dir 4 quad analog add cap. to set fre - quency drive with analog signal not used but gnd greater than 50% high for a low input greater than 50% high for a high input analog input operation the SA56 can operate with analog or digital inputs. in the analog mode, the capacitor from cpwm to gnd (sig) sets the frequency of an internal triangular ramp signal. an analog input at the pwm pin is compared to the ramp to generate the duty cycle of the output. in analog mode, the digital input on the dir pin is ignored, though this pin should never be left foating. operating with digital inputs two and 4 quadrant operation are possible with the SA56 when driven with a digital pwm signal from a microcontroller or dsp. when using a digital modulation signal, tie the cpwm pin to gnd to disable the internal oscillator and ramp generator. when operating in the digital mode, pulse widths should be no less than 100ns and the switching frequency should remain less than 500khz. this will allow enough time for the output mosfets to reach their full on/off state before receiving a command to reverse state. 2 quadrant digital mode for sign/magnitude (2 quadrant) operation, two digital input signals are required. a digital pwm signal to the pwm pin can control the output duty cycle at one output pin with the other output pin held "high". the digital input on the dir pin will control direction by selecting the outputs that switch accord - ing to the pwm input. if dir is a logic "high", the a output will be held "high" and the b output will be switched as the inverse of the pwm input signal. if dir is logic "low", the b output will be held "high" and the a output will be switched. operating in 2 quadrant mode reduces switching noise and power dissipation, but limits the control of the motor at very low speed. a braking function can be achieved by holding the pwm input "low", which will turn both of the upper mosfets on, rapidly reducing the circulating current of the motor winding. 4 quadrant digital mode during 4 quadrant operation a single digital pwm input in - cludes magnitude and direction information. the digital pwm input signal is applied to the dir pin and the pwm/input pin is tied to "high". both pairs of output mosfets will switch in a locked anti-phase fashion from 0-100% duty cycle. with a 50% duty cycle the average voltage of each output will be half of vs, and the differential voltage applied to the load will be zero. four quadrant operation allows smooth transitions through zero current for position servos and low speed ap - plications. power dissipation is slightly higher since all four output mosfets switch every cycle. npevmbujpotjhobm
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apex microtechnology corporation ? telephone (520) 690-8600 ? fax (520) 888-3329 ? orders (520) 690-8601 ? email prodlit@apexmicrotech.com 7 p r e l i m i n a ry this data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. all specifcations are subject to change without notice. a a ape icrotechnology orp. protection circuits thermal and short circuit protection are included in the SA56 to prevent damage during fault conditions. high current protection circuits will sense a direct short from either output to gnd or vs as well as across the load. the thermal protec - tion will engage when the temperature of the mosfets reach approximately 160c. the fault output pin will go "high" if either protection circuits engages and will place all mosfets in the "off" state (high impedance output). the sc or t lim output will also go "high", to indicate which of the protection features has been triggered. the fault going high disables the 4 output transistors. to reset the fault condition, cycle the v dd power or bring the disable pin "high" then "low". the most severe condition for any power device is a direct, hard-wired ("screwdriver") short from an output to ground. while the short circuit protection will latch the output mosfets within 250ns (typical) the die and package may be required to dissipate up to 600 watts of power until the protection is engaged. this energy can be destructive, particularly at higher operating voltages, so good thermal design is critical if such fault tolerance is required of the system. programmable current limit the isen pin sources a current proportional to the forward output current of the active p channel output mosfet. the proportionality is 300a (nom) per ampere of output current. the isen output is blocked during the switching transitions when current spikes can be signifcant. to create a programmable current limit, connect a resis - tor from isen out to gnd. when the voltage across this resistor exceeds internally generated 2.75v threshold, all 4 output mosfets will be turned off for the remainder of the switching cycle. a 2.75k resistor will set the current limit to approximately 5 amps. the isen output can also be used for maintaining a current control loop in torque motor applications. SA56 current sense linearity calculation the current sense linearity is calculated using the method described below: a) defne straight line (y = mx + c) joining the two end data points where, m is the slope and c is the offset or zero crossover. calculate the slope m and offset c using the extreme data points. assume isense in the y axis and iload in the x axis. b) calculate linear isense (or ideal isense value, is ideal ) using the straight line equation derived in step (a) for the iload data points. c) determine deviation from linear isense (step (b)) and actual measured isense value (is actual ) as shown below: ic rev c errata information this document describes the errata information for SA56 rev c full h-bridge dc motor driver. rev c parts can be identifed by date code 0206 marked on the ex package. errata number and date description impact 1 dated: 3/3/06 tlim pin: this pin is mod - ified to serve as a flag for any fault occur - rence including short-circuit, over current and over tem - perature. impact: grounding the tlim pin disables all fault protec - tion mechanisms in the SA56 including sc, over current and over temp. this pin should be left foating at all times un - less the user desires to disable all protection mechanisms. note: the errata items described in the table above are strictly for beta samples and will be rectifed to conform to SA56u specifcations for the production parts. %fwjbujpogspn-jofbsjuz *4 *%&"- m*4 "$56"- *4 *%&"- r


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